Ajith Pasqual
B.Sc. Eng. (Moratuwa), M.Eng. (Tokyo), Ph.D. (Tokyo), MIEEE, MACM

Senior Lecturer,
Department of Electronic & Telecommunication Engineering,
University of Moratuwa,
Sri Lanka.

Department of Electronic & Telecommunication Engineering,
University of Moratuwa,
Moratuwa 10400
Sri Lanka.
Tel: (+94)-11-2650634-6,2650301 Ext. 3300, 3301
Tel: (+94)-11-265055 (Direct)
Fax: (+94)-11-2650652 Attention: Dr. Ajith Pasqual

Email: pasqual @ ent.mrt.ac.lk

Tel: (+94)-11-2816850

Research Publications Teaching Family


Research Students:

Upul Ekanayaka (Ph.D)
Amila Cabral (Ph.D)
Varuna Jayasiri (M.Phil)
Thilina Ambagahawatta (M.Phil)
Samunda Perera (M.Sc) - Completed
Samoda Gamage (M.Sc) - Completed
Sunimal Wickramasuriya (Final Year Undergraduate) - Completed
Lakshitha Wijesinghe (Final Year Undergraduate)- Completed
K. Kamalavasan and Yasas Seneviratne(Final Year Undergraduates) - ongoing (Neural Net Processor)

Research Grants:
  1. Senate Research Committee (SRC) Grant - 2012 - Hardware Acceleration for Software Based Systems - Ajith Pasqual
  2. National Research Council (NRC) 2012-018 - Machine Vision Based Intelligent Surveillance System for Expressways - Ajith Pasqual, Ranga Rodrigo and Jayathu Samarawickrama
Research Groups:

HEVC Video Compression

Real Time 4K HEVC Decoder on FPGA

Manupa Karunarathne, Maleen Abeydeera, Kalana De Silva, Geethan Karunarathne - Undergraduate Final Year Project - Completed

M. Abeydeera, M. Karunarathne, G. Karunaratne, K. De Silva and A. Pasqual, 4K Real Time HEVC Decoder on FPGA, IEEE Transactions on Circuits and Systems for Video Technology.pg 236-249, Volume 26, Issue 1, January 2016. (PDF)

Maleen Abeydeera, Ajith Pasqual, "HEVC Inverse Transform Architecture Utilizing Coefficient Sparsity", 27th IEEE Conference on Image Processing (ICIP 2015), Quebec, Canada (PDF)

HEVC Multi-View Codec

Kirshanthan S., Lajanugen L., Panagoda P.N.D., Wijesinghe L.P - Undergraduate Final Year Project - Completed

Kirshanthan S., Lajanugen L., Panagoda P.N.D., Wijesinghe L.P., De Silva D.V.S.X., and Pasqual A. A., "Layered Depth Image Based HEVC Multi-view Codec", Advances in Visual Computing - Volume 8888 of the series Lecture Notes in Computer Science pp 376-385 (Presented at 10th International Symposium on Visual Computing, Las Vegas, USA, December 2014) (PDF)

Real Time HD HEVC All Intra Encoder on FPGA

Sachille Atapattu, Namitha Liyanage, Nisal Menuka, Ishantha Perera - Undergraduate Final Year Project - Completed

Sachille Atapattu, Namitha Liyanage, Nisal Menuka, Ishantha Perera and Ajith Pasqual, "Real Time All Intra HEVC HD Encoder on FPGA", 27th IEEE International Conference on Application Specific Architectures and Processors 2016 (ASAP 2016), London, UK. (PDF)

Processor/SoC Architectures for High Performance and Energy Efficiency

Novel Architectures for Packet Classification

Packet Classification is the enabling function for many Internet functions like QoS and Security. In this research we propose a Classification engine architecture which exploits parallelism to increase throughput. The architecture also make use of the Temporal locality observed in Internet traffic positively by employing Popular Rule Caching mechanism to increase the classification throughput. We also introduce Rule Splitting mechanism to increase the accuracy of the rule caching mechanism. Simulation results revealed that the architecture is capable of achieving a throughput of more than 200Gbps when lowest amount of temporal locality is present for worst case packet size of 40 bytes.

S. Gamage, A. Pasqual, High performance parallel scalable packet classification architecture with Popular Rule Caching, 18th IEEE International Conference on Networks (ICON 2012) (PDF)

Energy Efficient General Purpose Vision Processor Architecture for Mobile Devices

The main objective of this research is to develop an energy efficient processor for processing video (Vision Processor) that achieves a balance between power consumption and performance.

Amila Cabral - Graduate Student - Ph.D

Novel Processor Architectures for Concurrent Video Stream Processing

Thilina Ambagahawatta - Graduate Student - M.Phil

A Generalized Pre-Processing and Feature Extraction Platform for Scalp Electroencephalography (EEG) Signals on FPGA

Brain-computer interfaces (BCIs) require real-time feature extraction for translating input EEG signals from a user into a final command or decision. Owing to the inherent difficulties in EEG signal processing and neural decoding, many of the feature extraction algorithms are computationally demanding. Presently, software packages do exist to perform real-time feature extraction and classification of EEG signals. However, the requirement of a computer is a major drawback in bringing these technologies to the home user affording ease of use. This project proposes the FPGA design of a generalized platform that provides a set of predefined features and pre-processing steps that can be configured by the user for BCI applications. This will enable a gradual transition from software to hardware for such systems that will consume less power and be capable of much faster signal processing. Some basic pre-processing steps such as signal averaging, powerline noise cancellation etc. along with a set of common features (both linear and nonlinear) such as band energies, power spectral density values, autoregressive coefficients etc. will be provided by the platform. Additionally, since a trend of combining different types of biomedical signals for various purposes is emerging, we will seek to integrate ECG and EEG feature extraction in this system.

Sunimal Wickramasuriya, Lakshitha Prabath Wijesinghe - Undergraduate Research Project L.P Wijesinghe, D.S Wickramasuriya, and Ajith A. Pasqual, "A Generalized Preprocessing and Feature Extraction Platform for Scalp EEG Signals on FPGA", IEEE International Conference on Biomedical Engineering and Sciences (ICBES) 2014, pg. 137-142, Kuala Lampur, Malaysia (PDF)
Hardware Acceleration of Software Based Systems

Hardware Acceleration for Cloud Computing

Upul Ekanayaka - Graduate Student - Ph.D.
K.U.B. Ekanayaka, Ajith Pasqual, "FPGA Based Custom Accelerator Architecture Framework for Complex Event Processing", TENCON 2014 - 2014 IEEE Region 10 Conference, Pg. 1 – 6, Bangkok, Thailand, (PDF)

Machine Vision, Video Coding

Realtime Handheld MonoSLAM in Dynamic Environments

Traditional monoSLAM assumes stationary landmarks making it unable to cope up with dynamic environments where moving objects are present in the scene. This paper presents the parallel implementation of monoSLAM with a set of independent EKF trackers where stationary features and moving features are tracked separately. The difficult problem of detecting moving points from a moving camera is addressed by the epipolar constraint computed by using the measurement information already available with the monoSLAM algorithm. While doing so SLAM measurement outlier rejection is also performed. Results are presented to verify and highlight the advantages of our approach over traditional SLAM.

Samunda Perera, Ajith Pasqual, Towards Realtime Handheld MonoSLAM in Dynamic Environments, International Symposium in Visual Computing 2011, pp 313-324 ( PDF )

Probabilistic Model for Computationally Efficient Real-time Robust Object Tracking using Multiple Cues

Real-time object tracking in unconstrained environments can be made reliable by using different cues. Use of multiple visual cues, though reliable, requires more computational resources for analysis. This research proposes a novel model to integrate multiple trackers for efficient and robust object tracking by switching among cues in short intervals based on the environment, instead of analyzing all of them. Single cue trackers based on binary features, optical flow, and color, were used to test the model. It is shown that the model consistently picks the most suitable tracker depending on the environment.

Parinda Jayasiri - Graduate Student - M.Phil

Multi-View HEVC Encoder (Co Supervision with Dr. Varuna De Silva - University of Surrey)

Pre standard Algorithm Development for Multi View HEVC Encoder

Lajanugen Logeswaran, Lakshitha prabath Wijesinghe, Nisal Panagoda, Kirshanthan Sundararajah - Undergraduate Final Year Project
Software Defined Networking

OpenFlow Aware Network Processor (Undergraduate Final Year Project)

W.A.T.M. Dananjaya, S. Iddamalgoda, K.G.P.H Kariyawasam, W.M.V.B. Wijekoon
V. B. Wijekoon, T. M. Dananjaya, P. H. Kariyawasam, S. Iddamalgoda, Ajith Pasqual, "High Performance Flow Matching Architecture for OpenFlow Data Plane", to be presented on 2016 IEEE Conference on Network Function Virtualization and Software Defined Networks, November 2016, Palo Alto, California, USA.
Ongoing Final Year Undegraduate Projects

High Performance RISC-V Base ISA Processor (Plug-in Replacement for MicroBlaze on FPGA)
Nimashani Perera, Ravi Tharaka, Mojith Thilakasiri, Yasas Seneviratne

Ultra Low Power RISC-V Base ISA Processor for IOT
Amila Chandimal Jayawickrama, A.A.S.D. Maduwantha, Isuru Rathnayaka, Rajith Lakshan Rathnayake

JPEG-XT IP Core Development
Aravinth, Kamalavasan, Natheesan, S.Gowthaman

JPEG2000 IP Core Development
V.G.T.Gayan, Malan Evans, Randika prabudda, Sajith vishwaranga

Hybrid SDN Controller
Binal Chathuranga, Kosala Perera, Chamika Ramanayake, Udesh

Publications: [Recent list]

Samoda Gamage and Ajith Pasqual, High Performance Parallel Packet Classification Architecture with Popular Rule Caching, 18th IEEE International Conference on Networks (ICON), Singapore, 2012

K.N.S. Perera and A.A. Pasqual Towards Real-time Handheld MonoSLAM in Dynamic Environments, in Springer Lecture Notes in Computer Science Vol. 6938 September 2011,

Amila Cabral and Ajith Pasqual, 'FPGA Implementation of Normalized Cross-Correlation for Real-time Template Matching in Dynamic Search Windows', 17TH ERU Research Symposium, 2011

H.M.R.D. Lakshan, C.M. Liyanage, T.T.D. Perera, D.S.S. Wijesundara and A.A. Pasqual High Performance Software Application Acceleration using Field Programmable Gate Arrays In Proceedings of ERU Symposium, November 2010.

M. Samarawickrama, R. Rodrigo and A. Pasqual HLS Approach in Designing FPGA -Based Custom Coprocessor for Image Preprocessing, In Proceedings in International Conference in Information and Automation for Sustainable Systems (ICIAfS) 2010.

H.M.K.G.S. Jayasumana, T.M.U.A.S. Thennakoon, C.M.R.B. Chandrasekara, , M.T. Sandaruwan, N. Dayananda and A.A. Pasqual A Stand-Alone ECG Abnormality Detector, in Proceedings of International Conference in Information and Automation for Sustainable Systems (ICIAfS) 2010.

L. Liyanage, A. Pasqual and Clayton R. Wright, 2010, Lessons Learned in Managing ICT Systems for Online-Learning, In Proceedings in Fifth Conference of Learning International Networks Consortium (LINC) 2010

M. Samarawickrama, A. Pasqual and R. Rodrigo FPGA-Based Compact and Flexible Architecture for Real-Time Embedded Vision Systems, In International Conference on Industrial and Information Systems (ICIIS)} 2009.

R. Panangalage, A. Pasqual, Impact of ICT on learning and teaching ; In IEEE International Symposium on Technology and Society, 2008. 26-28 June 2008 Page(s): 1 - 10

B.M.D.P Bandara , J.T.C Gunasekara, K. U.K. Welliwatta, W.A.I.M.Wickramasinghe, A. Pasqual, D. Dias, Cellular Intercom, In Proceedings of 9th International Information Technology Conference 2008.

H.K.D Piyaratne, D.R.S Warnakula., K.A Nadeesha, O.P.N Perera, A.A Pasqual, Image Guided Tool for Neurosurgery In Proceedings of International Conference in Information and Automation, December 2006

S. Kodagoda, E.A.S.M. Hemachandra, P.A.A.R. Pannipitiya, L.S. Bartholomeuz, and A.A.Pasqual, Minimal Invasive Headband for Brain Computer Interfacing and Analysis In Proceedings of International Conference in Information and Automation}, December 2006

M.G.B. Sumanasena , J.G. Samarawickrama, A.A.Pasqual, Mobile Stereo Camera Platform for Active Vision In proceedings of International Conference on Industrial and Information Systems , August 2006

Sumanasena M.B., Samarawickrama J.G. , Pasqual A. A., Mobile Stereo Camera Platform for Active Vision - FPGA Controller", In Proceedings of IEEE International Conference on Information and Automation , December 2005

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Last Modified: Sunday, 16-Oct-2016 00:50:09 IST